Exemplary embodiments of the present invention relate to a filter circuit which is applicable to integrated circuits using a filter.
Digital systems may use digital filters, where a low pass filter is frequently used. A low pass filter is used to output a low frequency signal, and may be designed for signal processing for a specific frequency band. In addition, a low pass filter is used to improve stability in terms of control and to reduce jitter.
FIG. 1 is a configuration diagram of a conventional digital phase locked loop (PLL) that includes a filter.
Referring to FIG. 1, the digital PLL includes a phase detector 110, a filter 120, an oscillator 130, and a divider 140. The filter 120 is used to filter an up/down signal UP/DN outputted from the phase detector 110 to thereby remove jitter or noise components from the up/down signal UP/DN, where the phase detector 110 may decrease a frequency of the up/down signal UP/DN. Here, due to limitations in the processing speed of the oscillator 130 and a delay of the feedback loop including the divider 140, the high frequency up/down signal UP/DN is to be converted into a low frequency signal. Without the filter 120, serious jitter may occur at the output of the oscillator 130, or an output signal CLK_OUT of the digital PLL may diverge.
Here, the filter 120 reduces jitter and noise and ensures a stable operation of the PLL. However, excessive filtering by the filter 120 reduces the operating speed of the PLL and increases a locking time of the PLL.
Thus, while the filter 120 ensures a stable operation of a circuit (a PLL or other circuits) to which the filter is applied, it also reduces the operating speed of the circuit to which the filter is applied.